A circuit for correction of the duty cycle value of a digital data signal is known from the document “CMOS Digital Duty Cycle Correction Circuit for Multi-Phase Clock” (Y. C. Jang, S. J. Bae, H. J. Park; “Electronics Letters” 18 Sep. 2003, Vol. 39, No. 19, pages 1383 to 1384). The already known circuit has a duty cycle correction device with a rising edge detector (rising edge generator) and a falling edge detector (falling edge generator). The falling edge detector is arranged upstream of a controllable phase shifter, which can be driven by means of a control signal. The controllable phase shifter is driven by a duty cycle detector, which measures the duty cycle value of the data signal at the signal output of the duty cycle correction device and transmits a control signal to the controllable phase shifter such that the data signal at the signal output of the duty cycle correction device reaches a predetermined duty cycle value.
The duty cycle detector in the already known circuit has two current integrators which are connected in parallel. A comparator is connected to the output of the two current integrators, and is followed by a digital counter. The two current integrators are analogue components.